Vector processor for processing recurrent equations at a high speed

ABSTRACT

An improved vector processor for processing a modified recurrent equation: a i  =a i-2  ×b i-1  ×b i  +b i  ×c i-1  +c i , where i is an integer: i=1, 2, 3, . . . , n, at a high speed. The vector processor includes a data distribution circuit (40a, 40b), at least one odd term calculation circuit (10A, 10AA), and at least one even term calculation circuit (10B, 10BB). The odd term calculation circuit calculates odd terms of the modified recurrent equation: a j  =(a j-2  ×b j-1  ×b j )+(b i  +c j-1 )+c j , where j is an odd integer. The even term calculation circuit calculates even terms of the recurrent equations: a k  =(a k-2  ×b k-1  ×b k )+(b k  ×c k-1 )+c k , where k is an even integer. The data distribution circuit receives an initial, data a 0  and input vector (operand) data (b i ) and (c i ), and distributes that data to the odd and even term calculation circuits in a predetermined manner so that the above odd and even terms are calculated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data processing system, moreparticularly, to a vector processor for processing recurrent equationsat a high speed.

2. Description of the Related Art

Recent remarkable advances in computer technologies have improved theoperation speed of supercomputers by providing, for example, vectorprocessors. These vector processors are used to carry out scientificcalculations, such as a numerical solution of linear equations or anumerical solution of differential equations, etc., at a very highspeed.

In scientific technical calculations, the following recurrentoperational algorithm (or recurrent equation) is frequently used tosolve first order linear equations by a numerical solution, ordifferential equations by a difference method, etc.

    a.sub.i =a.sub.i-1 ×b.sub.i +c.sub.i                 ( 1)

where, i=1, 2, 3, . . . , n

This operational algorithm (1) shows the recurrent relationship betweena datum a_(i) and a datum a_(i-1). In general, the operation of theabove recurrent equation is not suitable for calculations by the vectorprocessor at a high speed, since the datum a_(i-1) is used again tocalculate the datum a_(i), i.e., the term a_(i) must be calculated aftercalculation of the term a_(i-1). Therefore, prior art vector processorscannot calculate the recurrent equations at a high speed. The prior artvector processor used for handling recurrent equation will be describedlater with reference to the drawings.

Nevertheless, there is a strong demand for a capability to calculate therecurrent equation at a high speed by using a vector processor, sincemany recurrent equations are used in the scientific technicalcalculation field.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a vector processorwhich can process recurrent equations at a high speed.

Another object of the present invention is to provide a vector processorhaving a simple circuit construction which can be easily formed.

According to the present invention, there is provided a vector processorincluding a vector instruction control unit for controlling vectorinstructions, a vector storage access unit for accessing input vectordata and calculated data to a main storage unit, a vector calculationunit for calculating vector data under the control of the vectorinstruction unit, and a data distribution unit for transferring databetween the vector data access unit and the vector calculation unit,characterized in that the vector processor comprises a vectorcalculation unit including at least one odd term calculation circuit andat least one even term calculation circuit, and a data distribution unitoperatively connected to and cooperative with said vector calculationunit, to process a modified recurrent equation. Each odd termcalculation circuit is formed to calculate odd terms of the modifiedrecurrent equation and includes an adding circuit, a multiplicationcircuit, at least one data storage circuit holding a calculated oddterm, and at least one feedback line for feeding back the calculated oddterm to the multiplication circuit and/or the adding circuit through thedata storage circuit. Each even term calculation circuit is formed tocalculated even terms of the recurrent equation and includes anotheradding circuit, another multiplication circuit, at least one other datastorage circuit holding a calculated even term, and at least one otherfeedback line for feeding back the calculated even term to anothermultiplication circuit and/or another adding circuit through anotherdata storage circuit. The data distribution unit includes a first datasetter for outputting zero, a second data setter for outputting one,first to sixth selectors for selecting input operands used forcalculating the recurrent equation, constant data 0 and 1 from thesetters, and the calculated odd and even terms, and a selector controlcircuit for controlling the selectors in a predetermined manner definedby the modified recurrent equation, to supply selected data to the oddand even term calculation circuits.

The recurrent equation expressed by the formula (1) can be modified asshown in the following formula, when a first-order development isapplied: ##EQU1##

When an index i is even, for example, an even index k=2, 4, and 6.##EQU2##

When an index i is odd, for example, an odd index j=1, 3, 5, and 7.##EQU3##

Note that there is no direct recurrent relationship between the terms a₂and a₀, a₄ and a₂ , and a₆ and a₄. Similarly, there is no directrecurrent relationship between the terms a₃ and a₁, a₅ and a₃, and a₇and a₅. Accordingly, the odd term calculation circuit can calculate oddterms a_(j) without a delay by the direct recurrence, and the even termcalculation circuit can calculate even terms a_(k) without a delay bythe direct recurrence, and thus contribute to a high speed calculationof the recurrent equations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a high speed data processing system whichincludes a vector processor of the present invention;

FIG. 2 is a block diagram of a general vector processor used in the dataprocessing system shown in FIG. 1;

FIG. 3 is a circuit diagram of a prior art vector processor;

FIG. 4 is an operation timing chart of the vector processor shown inFIG. 3;

FIG. 5 is a circuit diagram of an embodiment of a vector processor inaccordance with the present invention;

FIG. 6 is an operation timing chart of the vector processor shown inFIG. 5;

FIG. 7 is a circuit diagram of another embodiment of a vector processorin accordance with the present invention; and,

FIG. 8 is an operation timing chart of the vector processor shown inFIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing preferred embodiments of a vector processor inaccordance with the present invention, a high speed data processingsystem in which the vector processor is provided will be described withreference to FIG. 1.

In FIG. 1, the high speed data processing system consists of a mainstorage unit (MSU) 1, a main storage control unit (MSCU) 1, aninput/output (I/O) processing unit 3, a scalar data processing unit(scalar processor) 4, and a vector data processing unit (vectorprocessor) 5. The I/O processing unit 3 inputs data to be calculated andoutputs data calculated at the scalar processor 4 and/or the vectorprocessor 5. The MSU 1 stores the input data and the calculated data.The scalar processor 4 controls all calculations. When operationcommands concern a scalar operation, the scalar processor 4 executes ascalar data calculation. When operation commands concern a vectoroperation, the scalar processor 4 transfers control to the vectorprocessor 5 to carry out a vector calculation at the vector processor 5.Namely, the vector processor 5 is triggered by the scalar processor 4when the vector calculation is requested, and carries out the vectorcalculation. The MSCU 2 controls the data flow among the MSU 1, the I/Oprocessing unit 3, the scalar processor 4, and the vector processor 5.

A general configuration of the vector processor 5 shown in FIG. 1 isshown in FIG. 2. In FIG. 2, the vector processor 5 includes a vectorinstruction control unit (VICU) 51 having a decoder and a controlregister; a vector storage access unit (VSAU) 52 having a vector addressgenerator, an access data processor and a vector register unit; a datadistribution unit 54; and a vector calculation portion having an addingand subtracting unit 55, a multiplication unit 56, and a division unit57. The VICU 51 receives data control instructions from the scalarprocessor 4. The control register saves control data of the data controlinstructions. The decoder decodes the data control instructions. TheVSAU 52 transfers data between the MSU 1 and the vector calculationportion through the MSCU 2 and the data distribution unit 54. The vectoraddress generator generates addresses for accessing data in the MSU 1 inaccordance with the decoded instructions. The access data processorcontrols data between the MSU 1 and the vector register unit. Data to beused for a vector calculation are once stored in the vector registerunit. Also, data calculated at the vector calculation portion are storedin the vector register unit. The data distribution unit 40 distributesthe data from the vector register unit to supply the same to theadding-subtracting unit 55, the multiplication unit 56, and the divisionunit 57 in accordance with the decoded instruction. The units 55, 56,and 57 are operatively connected to perform the vector calculation. Thevector calculated data are stored in the vector register unit throughthe data distribution unit 40, thereafter, are stored in the MSU 1.

A prior art of a vector processor will be described with reference toFIGS. 3 and 4. FIG. 3 shows an elementary circuit diagram for processingthe recurrent equation discussed above. FIG. 4 shows an operation timingchart of the vector processor of FIG. 3.

In FIG. 3, the vector processor includes a selector 30, registers 14, 15and 16, a multiplication circuit 17, registers 18 and 19, an adder 110,a register 112, and a feedback line 31 connected between an outputterminal of the register 112 and an input terminal of the selector 30.These circuit components are a part of the vector calculation portionshown in FIG. 3. The multiplication circuit 17 calculating a term:a_(i-1) ×b_(i). The adder 110 adds c_(i) and the result from themultiplication circuit 17. On one hand, the added data is fed back tothe multiplication circuit 17 through the feedback line 31, the selector30 and the register 15 to use a next term calculation, and on otherhand, the added data is output to the vector register unit. The selector30 outputs an initial vector data a₀ at an initial time. The registers14, 15, and 16, the registers 18 and 19, and the register 112 areprovided to hold the data, respectively. The register 112 and thefeedback line 31 are provided to feed back the calculated data a_(i) tothe register 15 for calculating a next term a_(i+1).

Note that, since subtraction and division are not needed to calculatethe recurrent equation, a subtracting circuit and a division circuit areomitted in FIG. 3.

The operation of the vector processor shown in FIG. 3 will be describedin more detail with reference to FIG. 4.

When an integer i indicating an index of the recurrent equation is 1,the recurrent equation is expressed as follows:

    a.sub.1 =a.sub.0 ×b.sub.1 +c.sub.1

Thus, at the operation cycle 01, initial data c₁, a₀, and b₁ are loadedinto the registers 14, 15, and 16 from the vector register unit shown inFIG. 2. Then, a multiplication of (a₀ ×b₁) is carried out at themultiplication circuit 17. At the operation cycle 02, the data c₁ loadedin the register 14 is transferred to the register 18. Also, the datacalculated at the multiplication circuit 17 is transferred to theregister 19. Thereafter, the adder 110 adds the data c₁ and the datastored in the register 19, to obtain the result a₁. At the operationcycle 03, the result a₁ is stored in the register 112, and is thenoutput to the vector register unit shown in FIG. 2 through the datadistribution unit 54.

At the operation cycle 04, the next vector data b₂ and c₂ are loadedinto the registers 16 and 14 through the vector register unit. At thesame time, the data a₁ stored in the register 112 is loaded into theregister 15 through the feedback line 31 and the selector 30. During theoperation cycles 04-06, a calculation of a next term: a₂ =a₁ ×b₂ +c₂ iscarried out.

Similarly, during the operation cycles 07=09, a calculation of a term:a₃ =a₂ ×b₃ +c₃ is carried out. During the operation cycles 10-12, acalculation of a term: a₄ =a₃ ×b₄ +c₄ is carried out. During theoperation cycles 13-15, a calculation of a term: a₅ =a₄ ×b₅ +c₅ iscarried out.

As described above, a calculation time for obtaining one term a_(i)requires three operation cycles. If 100 terms of vector processing arerequired, 300 operation cycles are needed to obtain calculated data of100 recurrent equations. Accordingly, a high speed operation forcalculating the recurrent equations, in particular, for high orderrecurrent equations, can not be achieved by the prior art vectorprocessor.

The above defect depends upon a recurrence relationship wherein acalculation of a term a_(i) must be carried out after a calculation of ajust previous term a_(i-1). Thus, the prior art vector processor is madeidle in order to calculate the just previous term before proceeding to acalculation of a next term. Therefore, even though the vector processorcorrectly solves the above recurrent equation, the vector processorstill suffers from the above described low speed operation.

The present invention solves the above defect by modifying the recurrentequation.

The recurrent equation described above can be modified as follows:##EQU4## where, i is an integer indicating an index, i=1, 2, 3, . . . ,n a_(i) are calculated vector data, b_(i) are input vector data, andc_(i) are input vector data.

From the formula (2), it is recognized that there is no direct recurrentrelationship between a term a_(i) and another term a_(i-2) like thedirect recurrent relationship between a term a_(i) and another terma_(i-1) discussed above. According to the above formula (2), acalculation of the term a_(i) is not affected by a calculation of a justprevious term a_(i-1). The term a_(i-2) is already calculated two stepsprior to a calculation of the term a_(i), and thus a calculation of theterm a_(i) can be carried out immediately without a delay in thecalculation of the just previous term a_(i-1). But, the above conceptcannot be realized unless odd terms and even terms are separatelyoperated.

When an index i is even, an even index k is used, and the above formula(2) is expressed as follows: ##EQU5##

When an index i is odd, an odd index j is used, and the above formula(1) is expressed as follows: ##EQU6##

Note that, since there is no direct recurrent relationship between, forexample, the terms a₀ and a₂, the terms a₂ and a₄, the terms a₄ and a₆,the terms a₁ and a₃, or the terms a₃ and a₅, except for the terms a₀ anda₁, a pair of terms, for example, a₃ and a₄, can be calculated inparallel. This enables a high speed vector data calculation.Nevertheless, a calculation of the terms a₃ and a₄ must be carried outafter the calculation of the terms a₁ and a₂.

A first embodiment of a vector processor in accordance with the presentinvention will be specifically described with reference to FIG. 5.

In FIG. 5, the vector processor includes a data distribution circuit40a, and a vector data calculation unit consisting of an odd termcalculation circuit 10A and an even term calculation circuit 10B.

The data distribution circuit 40a is provided in the vector registerunit shown in FIG. 2, the odd term calculation circuit 10A, and the eventerm calculation circuit 10B, to supply an initial operand (data) a₀,and operands (input vector data) b_(i) and c_(i) to the odd and eventerm calculation circuits 10A and 10B, in a predetermined mannerdiscussed later. The data distribution circuit 40a also receives oddterm data a_(j) calculated at the odd term calculation circuit 10A andeven term data a_(k) calculated at the even term calculation circuit10B, and outputs the same to the vector register unit.

The data distribution circuit 40a includes a selector control circuit41a, a B-buffer (B-BUFF) 42 of a first-in first-out type (FIFO) buffer,for first inputting the operands b_(i) and first outputting the same,and a C-buffer (C-BUFF) 43, which is also a FIFO buffer, for firstinputting the operands c_(i) and first outputting the same. The datadistribution circuit 40a also includes selectors 46A, 47A, 48A, 46B,47B, and 48B. The data distribution circuit 40a further includes a zero(0) setter (not shown) for outputting zero to the selectors 46A and 46B,and a one (1) setter (not shown) for outputting one to the setters 47A,48A, 47B, and 48B.

The odd term calculation circuit 10A for calculating the odd terms a_(j)includes first stage registers 14A, 15A and 16A, a multiplicationcircuit 17A, second stage registers 18A and 19A, an adder 110A, a thirdstage registers 111A, a fourth stage register 112A, a first feedbackline 21A connected between an output terminal of the register 19A and aninput terminal of the selector 48A, and a second feedback line 22Aconnected between an output terminal of the register 112A and an inputterminal of the selector 46A, and a third feedback line 23A connectedbetween an output terminal of the register 111A and an input terminal ofthe selector 47A. Calculated odd terms a_(j) are sequentially outputfrom the register 111A to the vector register unit.

The registers 111A and/or 112A can be included in the data distributioncircuit 40a.

The even term calculation circuit 10B for calculating the even termsa_(k) has the same circuit construction as that of the odd termcalculation circuit 10A, because the operational algorithms are the samein both cases. Since both the odd and even term calculation circuits 10Aand 10B can have the identical construction, the design, production andmounting thereof on a printed circuit board (PCB) are greatlysimplified. Both of the odd and even term calculation circuits 10A and10B are operable independently and simultaneously.

The operation of the vector processor shown in FIG. 5 will be described.

Supposing that the operands a_(i), c_(i) and the initial operand a₀ arepreviously stored in the MSU 2 shown in FIG. 1, and the followinginstruction set is detected at the scalar processor 4, the scalarprocessor 4 transfers control of the operation to the vector processorshown in FIG. 5, triggering the vector processor.

                  TABLE 1                                                         ______________________________________                                        VL           A(O) TO VR00                                                     VL           B(I) TO VR01                                                     VL           C(i) TO VR02                                                     VCAL         A(i) = A(i - 1) × B(I) +C(i)                               VST          A(i) TO VR00                                                     ______________________________________                                         where, VL indicates a "Vector Load" instruction, VCAL indicates a "Vector     Calculation" instruction, VST indicates a "Vector Store" instruction A(i)     B(i) and C(i) correspond to a.sub.i, b.sub.i and c.sub.i, and VR00, VR01      and VR02 indicate vector registers 00, 01 and 02 in the vector register       unit shown in FIG. 2. Note, in this embodiment, each vector register has      memory capacity of 100 words.                                            

First, the vector storage access unit (VSAU) 52 shown in FIG. 2 loadsvector data a₀, b₁ -- b₁₀₀, and c₁ -- c₁₀₀ stored in the main storageunit (MSU) 1 into the vector registers VR00, VR01 and VR02 of the vectorregister unit through the main storage control unit (MSCU) 2, inresponse to the above "Vector Load" instruction, under the control ofthe vector instruction control unit (VICU) 51 shown in FIG. 2.

During the above vector data loading, a calculation of recurrentequation: a_(i) =a_(i-1) ×b_(i) +c_(i) at the circuit shown in FIG. 5,and a store of calculated data a_(i) into the vector register VR00 arecarried out, in response to the above "Vector Calculation" and "VectorStore" instructions, under the control of the VICU 51.

The calculated data a_(i) in the vector register VR00 can be stored inthe MSU 1 during the above operation.

Now, a detailed operation of the circuit of FIG. 5 will be describedwith reference to FIG. 6.

A calculation consists of an initial term calculation for calculatingthe initial terms a₁ and a₂, and a normal term calculation forcalculating subsequent terms, for example, a₃ and a₄, a₅ and a₆, etc.

First, the initial term calculation will be described.

Below TABLE 2 and TABLE 3 show data loaded into the registers 14A, 15A,16A and 111A, and the registers 14B, 15B, and 16B, and 111B under thecontrol of the selector control circuit 41a.

                  TABLE 2                                                         ______________________________________                                        OP        REG     REG          REG   REG                                      CYCLE     14A     15A          16A   111A                                     ______________________________________                                        01        c.sub.1 b.sub.1      a.sub.0                                        02                                                                            03                                                                            04        0       a.sub.0 × b.sub.1 + c.sub.1                                                          1                                              05                                                                            06                                   a.sub.1                                  ______________________________________                                    

                  TABLE 3                                                         ______________________________________                                        OP        REG     REG          REG   REG                                      CYCLE     14B     15B          16B   111B                                     ______________________________________                                        01        c.sub.1 b.sub.1      a.sub.0                                        02                                                                            03                                                                            04        c.sub.2 a.sub.0 × b.sub.1 + c.sub.1                                                          b.sub.2                                        05                                                                            06                                   a.sub.2                                  ______________________________________                                    

The data distribution circuit 40a loads initial operands a₀, b₁ and c₁therein; the operands b₁ and c₁ being stored in the B-BUFF 42 and theC-BUFF 43, respectively.

OPERATION CYCLE 01

At the operation cycle 01, the selector control circuit 41a controls theselectors 46A, 47A, and 48A to output the operands c₁, b₁, and a₀ to theregisters 14A, 15A, and 16A in the odd term calculation circuit 10A.These registers 14A, 15A, and 16A store the operands c₁, b₁, and a₀. Atthe same time, the selector control circuit 41a controls the selectors46B, 47B, and 48B to output the operands c₁, b₁, and a₀ to the registers14B, 15B, and 16B in the even term calculation circuit 10B. Theseregisters 14B, 15B, and 16B also save the operands a₀, b₁, and c₁.

In the odd term calculation circuit 10A, the register 16A outputs thesaved operand a₀ to the multiplication circuit 17A as a multiplicand,and the register 15A outputs the saved operand b₁ to the multiplicationcircuit 17A as a multiplier. Thus, the multiplication circuit 17Acalculates (a₀ ×b₁).

At the same time, in the even term calculation circuit 10B, the register16B outputs the saved operand a₀ to the multiplication circuit 17B as amultiplicand, and the register 15B outputs the saved operand b₁ to themultiplication circuit 17B as a multiplier. The multiplication circuit17B calculates (a₀ ×b₁).

OPERATION CYCLE 02

In the odd term calculation circuit 10A, data (a₀ ×b₁) calculated at themultiplication circuit 17A is transferred to the register 19A and savedtherein. The data c₁ saved at the register 14A is also transferred tothe register 18A and saved therein.

At the same time, in the even term calculation circuit 10B, data (a₀×b₁) calculated at the multiplication circuit 17B is transferred to theregister 19B and saved therein. The data c₁ saved at the register 14B istransferred to the register 18B.

Thereafter, in the odd term calculation circuit 10A, the adder 110A addsthe data (a₀ ×b₁) and the data c₁. As a result, the following first oddterm is obtained.

    a.sub.1 =a.sub.0 ×b.sub.1 +c.sub.1

Similarly, at the same time, in the even term calculation circuit 10B,the above first odd term a₁ is obtained by the adder 110B.

OPERATION CYCLE 03

In the odd term calculation circuit 10A, the calculated first odd terma₁ is transferred to the register 111A and saved therein.

Also, in the even term calculation circuit 10B, the calculated first oddterm a₁ is transferred to the register 111B and saved therein.

During the above operation, the data distribution circuit 40a loadsoperands (b₂, b₃, b₄) and (c₂, c₃, c₄) into the B-BUFF 42 and the C-BUFF43 from the vector registers VR01 and VR02, respectively.

Note that, although having obtained the first odd term a₁, the datadistribution circuit 40a does not output the same to the vector registerVR00 at this time, because a first even term a₂ has not been obtained.

OPERATION CYCLES 04-06

Until the first even term a₂ is obtained at the even term calculationcircuit 10B, the odd term calculation circuit 10A and the datadistribution circuit 40a cooperate to keep the data a₁ as is, and toprepare operands used for calculating a second odd term a₃.

As the operation cycle 04, the selector control circuit 41a controls theselectors 46A, 47A, and 48A to set zero data to the register 14A, thecalculated first odd term a₁ to the register 15A through the register111A and the feedback line 23A, and a data of one (1) to the register16A. As a result, at the operation cycle 04, the multiplication circuit17A calculates (a₁ ×1), and at the operation cycle 06, the adder 110Aadds the data (a₁ ×1) from the register 19A and the data of zero (0)from the registers 18A. Namely, the following dummy calculation iseffected.

    a.sub.1 =(a.sub.1 ×1)+0

During the above operation, at the operation cycle 05, the selectorcontrol circuit 41a controls the selectors 47A and 48A to set an operandb₃ to the register 15A, and an operand b₂ to the register 16A. The dataa₁ is transferred to the register 111A at the operation cycle 05, and isfurther stored in the register 112A at the operation cycle 06.

Conversely, in the even term calculation circuit 10B, the followingfirst even term a₂ is calculated by using the first odd term a₁calculated therein and saved in the registers 112B.

    a.sub.2 =(.sub.1 ×a.sub.2)+c.sub.2

For this purpose, at the operation cycle 04, the selector controlcircuit 41a controls the selectors 46B, 47B, and 48B to set the operandc₂ to the register 14B, the first odd term a₁ saved in the register 111Bto the register 15B through the feedback line 23B, and the operand b₂ tothe register 16B. At the operation cycle 05, the first even term a₂ isobtained at the adder 110B, and at the operation cycle 06, the firsteven term a₂ is stored in the registers 111B.

The data distribution circuit 40a transfers the pair of first odd andeven terms a₁ and a₂ to the vector register VR00 from the register 111Aand 111B.

The initial term calculation is thus completed.

The normal term calculation will now be described.

OPERATION CYCLES 03-09

First, a calculation of a second odd term a₃ in the odd term calculationcircuit 10A will be described.

Since the second odd term a₃ is defined by the following formula, theselector control circuit 41a controls the selectors 46A, 47A, and 48A toload data as shown in TABLE 4 into the registers 14A, 15A, and 16A atthe following operation cycles shown in TABLE 4.

    a.sub.3 =a.sub.1 ×(b.sub.2 ×b.sub.3)+b.sub.3 ×c.sub.3 +c.sub.3

                  TABLE 4                                                         ______________________________________                                        OP       REG            REG     REG                                           CYCLE    14A            15A     16A                                           ______________________________________                                        03       c.sub.3        b.sub.3 c.sub.2                                       04                                                                            05       --             b.sub.3 b.sub.2                                       06                                                                            07       b.sub.3 × c.sub.2 + c.sub.3                                                            a.sub.1 b.sub.2 × b.sub.3                       08                                                                            09                                                                            ______________________________________                                    

At the operation cycle 03, a multiplication value (b₃ ×c₂) is obtainedat the multiplication circuit 17A. At the operation cycle 05, a sum (b₃×c₂)+c₃ is obtained at the adder 110A. At the operation cycle 05, amultiplication value (b₂ ×b₃) is obtained at the multiplication circuit17A. At the operation cycle 07, a multiplication value (a₁ ×b₂ ×b₃) isobtained at the multiplication circuit 17A. At the operation cycle 08,the calculated data (a₁ ×b₂ ×b₃) is supplied to the adder 110A. Theabove second odd term a₃ is obtained at the adder 111A. The calculatedsecond odd term a₃ is saved at the register 111A at the operation cycle08. At the operation cycle 09, the second odd term a₃ saved in theregister 111A is transferred to the vector register VR00 and saved inthe register 112A.

In the above, the data al saved in the register 112A is fed back to theregister 14A through the feedback line 22A. Also, the data (b₂ ×b₃)saved in the register 19A is fed back to the register 16A through thefeedback line 21A. The sum (b₃ ×c₂)+c₃ stored in the register 111A isfed back to the register 15A through the feedback line 23A.

Similarly, the following second even term a₄ is obtained at the eventerm calculation circuit 10B.

    a.sub.4 =a.sub.2 ×b.sub.3 ×b.sub.4 +b.sub.4 ×c.sub.3 +c.sub.4

The selector control circuit 41a also controls the selectors 46B, 47B,and 47B to load the following data shown in TABLE 5 into the registers14B, 15B, and 16B.

                  TABLE 5                                                         ______________________________________                                        OP       REG            REG     REG                                           CYCLE    14B            15B     16B                                           ______________________________________                                        03       c.sub.4        b.sub.4 c.sub.3                                       04                                                                            05                      b.sub.4 b.sub.3                                       06                                                                            07       c.sub.3 × b.sub.4 + c.sub.4                                                            a.sub.2 b.sub.3 × b.sub.4                       08                                                                            09                                                                            ______________________________________                                    

At the operation cycle 09, the odd and even terms a₃ and a₄ aretransferred to the vector register VR00 in the vector register unit.

OPERATION CYCLES 06-12

Similarly, during the operation cycles 06-12, the following third oddand even terms a₅ and a₆ are obtained at the odd and even termcalculation circuits 10A and 10B. ##EQU7##

To achieve the above calculation, the selector control circuit 41acontrols the selectors 46A, 47A, 48A, 46B, 47B and 48B to load thefollowing data shown in TABLE 6 and TABLE 7 to the registers 14A, 15A,16A, 14B, 15B and 16B.

                  TABLE 6                                                         ______________________________________                                        OP       REG            REG     REG                                           CYCLE    14A            15A     16A                                           ______________________________________                                        06       c.sub.5        b.sub.5 c.sub.4                                       07                                                                            08       --             b.sub.5 b.sub.4                                       09                                                                            10       c.sub.4 × b.sub.5 + c.sub.5                                                            a.sub.3 b.sub.4 × b.sub.5                       11                                                                            12                                                                            ______________________________________                                    

                  TABLE 7                                                         ______________________________________                                        OP       REG            REG     REG                                           CYCLE    14B            15B     16B                                           ______________________________________                                        06       c.sub.6        b.sub.6 c.sub.5                                       07                                                                            08       --             b.sub.6 b.sub.5                                       09                                                                            10       c.sub.5 × b.sub.6 + c.sub.6                                                            a.sub.4 b.sub.5 × b.sub.6                       11                                                                            12                                                                            ______________________________________                                    

At the operation cycle 11, the odd and even terms a₅ and a₆ are obtainedat the adders 111A and 111B and are transferred to the vector registerVR00.

Other pluralities of pairs of odd and even terms are obtained in thesame way as described above.

A calculation of a pair of odd and even terms requires only threeoperation cycles, except for a calculation of the first odd and eventerms. This time is same as that of the prior art vector processor.According to the vector processor shown in FIG. 5, twice the amount ofdata can be obtained in three operation cycles, except for the initialcalculation. Thus, the vector processor shown in FIG. 5 doubles thecalculation performance compared with that of the prior art vectorprocessor, when many terms of the recurrent equations are to becalculated.

Another embodiment of the vector processor in accordance with thepresent invention will be described with reference to FIG. 7.

In FIG. 7, the vector processor includes a data distribution circuit 40band a vector data calculation unit consisting of an odd term calculationcircuit 10AA and an even term calculation circuit 10BB.

The data distribution circuit 40b is provided in the vector registerunit shown in FIG. 2, the odd term calculation circuit 10AA, and theeven term calculation circuit 10BB, to supply an initial operand a₀ andoperands (input data) b_(i) and c_(i) to the odd and even termcalculation circuits 10AA and 10BB in a predetermined manner, asdescribed later. The data distribution circuit 40b also receives a pairof odd term data a_(j) calculated at the odd term calculation circuit10AA and even term data a_(k) calculated at the even term calculationcircuit 10BB, and outputs the same to the vector register unit.

The data distribution circuit 40b includes a selector control circuit41b, the B-BUFF 42, the C-BUFF 43, buffer registers 51A and 52A,selectors 53A, 54A, and 55A, registers 51B and 52B, and selectors 53B,54B and 55B. The data distribution circuit 40b also includes the zerosetter and the one setter (not shown).

The odd term calculation circuit 10AA includes the first-stage registers14A, 15A, and 16A, the multiplication circuit 17A, the second-stageregisters 18A and 19A, the adder 110A, the third-stage register 111A,and a feedback line 24A connected between an output terminal of theregister 111A and an input terminal of the register 51A.

The even term calculation circuit 10BB has the same circuit constructionas that of the odd term calculation circuit 10AA.

The vector processor shown in FIG. 7 calculates the recurrent equationdefined by the formula (2). The odd term calculation circuit 10AA andthe data distribution circuit 40b cooperate to calculate the recurrentequations defined by the formula (4), and the even term calculationcircuit 10BB and the data distribution circuit 40b also cooperate tocalculate the recurrent equations defined by the formula (3).

The operation of the vector processor shown in FIG. 7 will bespecifically described with reference to FIG. 8, when the instructionset shown in TABLE 1 is given.

The operation of the MSU 1, the MSCU 2, the VICU 51, and the VSAU 52,shown in FIG. 2, is omitted, since the operation thereof issubstantially the same as that described above.

In FIG. 8, the operation cycles consist of initial operation cycles01-08, and normal operation cycles 04-11, 10-14, etc.

OPERATION CYCLE 01-08

The following TABLE 8 and TABLE 9 show data in the registers 14A, 15A,16A, and 111A, and data in the registers 14B, 15B, 16B, and 111B, duringthe initial operation cycles.

                  TABLE 8                                                         ______________________________________                                        OP      REG        REG        REG     REG                                     CYCLE   14A        15A        16A     111A                                    ______________________________________                                        01      0          b.sub.1    1                                               02      c.sub.1    0          b.sub.1                                         03      0          a.sub.0    1                                               04                                                                            05                                                                            06      b.sub.1 × 0 + c.sub.1                                                              1 × a.sub.0 + 0                                                                    1 × b.sub.1 + 0                           07                                                                            08                                    a.sub.1                                 ______________________________________                                    

                  TABLE 9                                                         ______________________________________                                        OP      REG        REG        REG      REG                                    CYCLE   14B        15B        16B      111B                                   ______________________________________                                        01      0          b.sub.2    b.sub.1                                         02      c.sub.2    c.sub.1    b.sub.2                                         03      0          a.sub.0    1                                               04                                                                            05                                                                            06      c.sub.1 × b.sub.2 + c.sub.2                                                        1 × a.sub.0 + 0                                                                    b.sub.1 × b.sub.2 + 0                     07                                                                            08                                     a.sub.2                                ______________________________________                                    

The selector control circuit 41b controls the selectors 53A, 54A, and55A to load data into the registers 14A, 15A, and 16A, as shown in TABLE8, and the selector control circuit 41b controls the selectors 53B, 54B,and 55B to load data into the registers 14B, 15B, and 16B, as shown inTABLE 9.

First, a calculation of the term a_(j) in the odd term calculationcircuit 10AA will be described.

OPERATION CYCLE 01

Data 0, b₁, and 1 are loaded into the registers 14A, 15B, and 16A, and acalculation of (b₁ ×1) is carried out at the multiplication circuit 17A.

OPERATION CYCLE 02

Data 0 and (b₁ ×1) are loaded into the registers 18A and 19A, and bothdata are added at the adder 110A, to obtain the result (b₁ ×1+0). At thesame time, data c₁, b₁ and 0 are loaded into the registers 14A, 15A, and16A, and a calculation of (b₁ ×0) is carried out at the multiplicationcircuit 17A.

OPERATION CYCLE 03

The data (b₁ ×1+0) is stored in the register 111A.

The data c₁ stored in the register 18A and the data (b₁ ×0) stored inthe register 19A are added at the adder 110A, to obtain the result (b₁×0+c₁). At the same time, data 0, a₀, and 1 are loaded into theregisters 14A, 15A, and 16A, and a calculation of (a₀ ×1) is carried outat the multiplication circuit 17A.

OPERATION CYCLE 04

The data (b₁ ×1+0) stored in the register 111A is transferred to theregister 51A. The data 0 stored in the register 18A and the data (a₀ ×1)stored in the register 19A are added at the adder 111A, to obtain theresult (a₀ ×1+0).

OPERATION CYCLE 05

The data (b₁ ×1+c₁) and (b₁ ×0+c₁) are sequentially loaded into theregisters 51A and 52A, respectively. The data (a₀ ×1+0) is stored in theregister 111A.

OPERATION CYCLE 06

The data (a₀ ×1+0) stored in the register 111A is transferred to theregister 15A, and the data (b₁ ×1+0) stored in the register 52A istransferred to the register 16A. As a result, the data (a₀ ×1+0)×(1×b₁+0) is obtained at the multiplication circuit 17A.

The data (b₁ ×0+c₁) stored in the register 51 is loaded into theregister 14A.

OPERATION CYCLE 07

The data (b₁ ×0+c₁) from the register 14A is loaded into the register18A.

The data (b₁ ×0+c₁) stored in the register 18A and the data (a₀×1+0)×(1×b₁ +0) stored in the register 19A are added at the adder 110A,to obtain the resulting data ##EQU8##

OPERATION CYCLE 08

The calculated data a₁ is stored in the register 111A and transferred tothe vector register VR00.

Next, a calculation of the term a₂ in the even term calculation circuit10BB will be described with reference to TABLE 9.

OPERATION CYCLE 01

Data 0, b₂, and b₁ are loaded into the registers 14B, 15B, and 16B, anda calculation of (b₁ ×b₂) is carried out at the multiplication circuit17B.

OPERATION CYCLE 02

Data 0, and (b₁ ×b₂) are loaded into the registers 18B and 19B, and bothdata are added at the adder 110B, to obtain the result (b₁ ×b₂ +0). Atthe same time, data c₂, c₁, and b₂ are loaded into the registers 14B,15B, and 16B, and a calculation of (c₁ ×b₁) is carried out at themultiplication circuit 17B.

OPERATION CYCLE 03

The data (b₁ ×b₂ +0) is stored in the register 111B. The data c₂ storedin the register 18B and the data (c₁ ×b₂) stored in the register 19B areadded at the adder 110B, to obtain the result (c₁ ×b₂ +c₂). At the sametime, data 0, a₁, and 1 are loaded into the registers 14B, 15B, and 16B,and a calculation of (a₀ ×1) is carried out at the multiplicationcircuit 17B.

OPERATION CYCLE 04

The data (b₁ ×b₂ +0) stored in the register 111B is transferred to theregister 51B. The data (c₁ ×b₂ +c₂) is stored in the register 111B. Thedata 0 stored in the register 18B and the data (a₀ ×1+0) stored in theregister 19B are added at the adder 110B to obtain the result (a₀ ×1+0).

OPERATION CYCLE 05

The data (c₁ ×b₂ +c₂) and (b₁ ×b₂ +0) are loaded into the registers 51Band 52B, respectively. The data (a₀ ×1+0) is stored in the register111B.

OPERATION CYCLE 06

The data (c₁ ×b₂ +c₂) is loaded into the register 14B.

The data stored in the register 111B is transferred to the register 15B,and the data (b₁ ×b₂ +0) stored in the register 52B is transferred tothe register 16B. As a result, data (a₀ ×1+0)×(b₁ ×b₂ +0) is obtained atthe multiplication circuit 17B.

OPERATION CYCLE 07

The data (c₁ ×b₂ +c₂) stored in the register 18B and the data (a₀×1+0)×(b₁ ×b₂ +0) are added at the adder 110B, to obtain the resultingdata. ##EQU9##

OPERATION CYCLE 08

The calculated data a₂ is stored in the register 111B and transferred tothe vector register VR00 together with the data a₁.

The initial calculation is terminated.

Now, the normal calculation will be briefly described. The normalcalculation is similar to the initial calculation, except for the dataloading and transferring. Thus, the following description is mainly ofthe data loading.

OPERATION CYCLE 04-11

During these cycles, the odd term a₃ and the even term a₄ arecalculated.

The following TABLE 10 and TABLE 11 show data in the registers 14A, 15B,16A and 111A, and data in the registers 14B, 15B, and 16B, and 111B.

                  TABLE 10                                                        ______________________________________                                        OP      REG        REG       REG      REG                                     CYCLE   14A        15A       16A      111A                                    ______________________________________                                        04      0          b.sub.3   b.sub.2                                          05      c.sub.3    c.sub.2   b.sub.3                                          06                                                                            07                                                                            08                                                                            09      b.sub.3 × c.sub.2 + c.sub.3                                                        a.sub.1   b.sub.2 × b.sub.3 + 0                      10                                                                            11                                    a.sub.3                                 ______________________________________                                    

                  TABLE 11                                                        ______________________________________                                        OP      REG        REG       REG      REG                                     CYCLE   14B        15B       16B      111B                                    ______________________________________                                        04      0          b.sub.4   b.sub.3                                          05      c.sub.4    c.sub.3   b.sub.4                                          06                                                                            07                                                                            08                                                                            09      b.sub.4 × c.sub.3 + c.sub.4                                                        a.sub.2   b.sub.3 × b.sub.4 + 0                      10                                                                            11                                    a.sub.4                                 ______________________________________                                    

OPERATION CYCLES 07-14

During these operation cycles, the odd term a₅ and the even term a₆ arecalculated.

The following TABLE 12 and TABLE 13 show data in the registers 14A, 15A,16A, and 111A, and data in the registers 14b, 15b, 16b, and 111B.

                  TABLE 12                                                        ______________________________________                                        OP      REG        REG       REG      REG                                     CYCLE   14A        15A       16A      111A                                    ______________________________________                                        07      0          b.sub.5   b.sub.4                                          08      c.sub.5    c.sub.4   b.sub.5                                          09                                                                            10                                                                            11                                                                            12      b.sub.5 × c.sub.4 + c.sub.5                                                        a.sub.3   b.sub.4 × b.sub.5 + 0                      13                                                                            14                                    a.sub.5                                 ______________________________________                                    

                  TABLE 13                                                        ______________________________________                                        OP      REG        REG       REG      REG                                     CYCLE   14B        15B       16B      111B                                    ______________________________________                                        07      0          b.sub.6   b.sub.5                                          08      c.sub.6    c.sub.5   b.sub.6                                          09                                                                            10                                                                            11                                                                            12      b.sub.6 × b.sub.5 + c.sub.6                                                        a.sub.4   b.sub.5 × b.sub.6 + 0                      13                                    a.sub.6                                 14                                                                            ______________________________________                                    

Other pluralities of pairs of odd and even terms can be calculated inthe same way as described above.

The present invention is not limited by the above embodiments. Forexample, in the above embodiments, first-order developed recurrentequations as expressed by the formulas (2) to (4) were described. Whenthe recurrent equation as expressed by the formula (1) is modified byusing a second-order development, the following formula is obtained.##EQU10##

Apparently, the above formula shows that there is no direct recurrentrelationship between the terms a_(i) and a_(i-3).

When an index i is odd, for example, an odd index j is 3 and 5, theabove formula is expressed as follows: ##EQU11##

When an index i is even, for example, an even index k is 4 and 6, theabove formula is expressed as follows: ##EQU12##

From the above formulas (6) to (9), two odd terms a₃ and a₅, and twoeven terms a₄ and a₆ can be simultaneously calculated at a same timing.Thus, the operation time is further shortened. In this embodiment, anodd term calculation circuit is formed to calculate two adjacent oddterms, for example, a₃ and a₅, at a same timing. Similarly, an even termcalculation circuit is formed to calculate two adjacent even terms at asame timing. A data distribution circuit is formed to distribute data tothe odd and even term calculation circuits so that the above formulascan be calculated.

The vector processor of the present invention can be applied to avariety of data processing systems.

What we claim is:
 1. A vector processor for processing a modified recurrent equation having a formula expressed, when first order developed, as a_(i) =a_(i-2) ×b₁₋₁ ×b_(i) +b_(i) ×c_(i-1) +c_(i), comprising:vector instruction control means for controlling vector instructions; main storage means for storing data; vector storage access means for accessing input vector data and calculated data to said main storage means; vector calculation means for calculating vector data under control of said vector instruction means, said vector calculation means includes at least one odd term calculation means for calculating odd terms of the modified recurrent equation according to the formulas

    a.sub.1 =a.sub.0 ×b.sub.1 +c.sub.1

    a.sub.j =a.sub.j-2 ×b.sub.j-1 ×b.sub.j +b.sub.j ×c.sub.j-1 +c.sub.j

where j is an odd integer, each odd term calculation means including a first adding circuit, a first multiplication circuit, at least one odd term data storage circuit for holding a calculated odd term, and at least one odd term feedback line for feeding back the calculated odd term to at least one of said multiplication circuit and said first adding circuit through said odd term data storage circuit; and at least one even term calculation circuit means for calculating even terms of the modified recurrent equation according to the formula

    a.sub.k =a.sub.k-2 ×b.sub.k-1 ×b.sub.k +b.sub.k ×c.sub.k-1 +c.sub.k

where k is an even integer, each even term calculation means including a second adding circuit, a second multiplication circuit, at least one even term data storage circuit for holding a calculated even term, and at least one even term feedback line for feeding back the calculated even term to at least one of said second multiplication circuit and said second adding circuit through said even term data storage circuit; and data distribution means, operatively connected to and cooperative with said vector calculation means to process the modified recurrent equation, said data distribution means including a first data setter for outputting zero; a second data setter for outputting one; a plurality of selectors for selecting input operands for calculating the recurrent equation, constant data 0 and 1 from said first and second data setters, and the calculated odd and even terms; and a selector control unit for controlling said plurality of selectors in a predetermined manner defined by the modified recurrent equation, to supply selected data to said odd and even term calculation means.
 2. A vector processor according to claim 1, wherein said odd and even term calculation circuits are independently and simultaneously operable to calculate at least one pair of adjacent odd and even terms of the current equation, at a same operation time.
 3. A vector processor according to claim 2, wherein said data distribution means further comprises:a first first-in/first-out type buffer for inputting and outputting a plurality of first operands as source multipliers or multiplicands; and a second first-in/first-out type buffer for inputting and outputting a plurality of second operands as source addends.
 4. A vector processor according to claim 3,wherein said at least one odd term feedback line of said odd term calculation means comprises first, second and third odd term feedback lines; wherein said odd term calculation means is formed so that (a) said first adding circuit receives an addend from a first selection of said plurality of selectors, (b) said first multiplications circuit receives a multiplier and a multiplicand from second and third selectors of said plurality of selectors, (c) said first adding circuit for receiving multiplied data from said first multiplication circuit, (d) said odd term data storage circuit receives addition data from said first adding circuit, (e) said first selector receives the constant data of zero, the second operand from said second buffer, and the addition data stored in said odd term data storage circuit through said second feedback line, (f) said second selector receives the constant data of one, the first operand, and the addition data through said third feedback line, and (g) said third selector receives the constant data of one, an initial data term, the first and second operands from said first and second buffers, and the multiplied data from said first multiplication circuit through said first feedback line; wherein said at least one even term feedback line of said even term calculation means comprises fourth, fifth and sixth feedback lines; and wherein said even term calculation means is formed so that (h) said second adding circuit receives an addend from a fourth selector of said plurality of selectors, (i) said second multiplication circuit receives a multiplier and a multiplicand from fifth and sixth selectors of said plurality of selectors, (j) said second adding circuit for receiving multiplied data from said second multiplication circuit, (k) said even term data storage circuit receives addition data from said second adding circuit, (l) said fourth selector receives the constant data of zero, the second operand from said second buffer, and the addition data stored in said even term data storage circuit through said fifth feedback line, (m) said fifth selector receives the constant data of one, the first operand, and the addition data through said sixth feedback line, and (n) said sixth selector receives the constant data of one, the initial data, the first and second operands from said first and second buffers, and the multiplied data from said second multiplication circuit through said fourth feedback line.
 5. A vector processor according to claim 4,wherein said odd term calculation means comprises:an odd first-stage first data storage circuit connected to said first selector, for temporarily storing data therefrom; odd first-stage second and third data storage circuits respectively connected between said second and third selectors and said first multiplication circuit, for temporarily storing data from said second and third selectors; an odd second-stage first data storage circuit connected between said odd first-stage first data storage circuit and said first adding circuit, for temporarily storing data from said odd first-stage first data storage circuit; an odd second-stage second data storage circuit having an input terminal connected to said first multiplication circuit and an output terminal connected to said first adding circuit and said first feedback line, said second-stage second data storage circuit temporarily storing the multiplied data from said first multiplication circuit; and an odd third-stage data storage circuit connected between said first adding circuit and said odd term data storage circuit and to said third feedback line, for temporarily storing the addition data from said first adding circuit, and wherein said even term calculation means comprises:even first-stage first data storage circuit connected to said fourth selector, for temporarily storing data therefrom; even first-stage second and third data storage circuits respectively connected between said fifth and sixth selectors and said second multiplication circuit, for temporarily storing data from said fifth and sixth selectors; even second-stage first data storage circuit connected between said even first-stage first data storage circuit and said second adding circuit, for temporarily storing data from said even first-stage first data storage circuit; even second-stage second data storage circuit having an input terminal connected to said second multiplication circuit and an output terminal connected to said second adding circuit and said fourth feedback line, said even second-stage second data storage circuit temporarily storing the multiplied data from said second multiplication circuit; and even third-stage data storage circuit connected between said second adding circuit and said even term data storage circuit and to said sixth feedback line, for temporarily storing the addition data from said second adding circuit.
 6. A vector processor according to claim 5,wherein, at an initial operation time,said odd term calculation means and said data distribution means cooperate to calculate the following terms

    a.sub.1 =a.sub.0 ×b.sub.1 30 c.sub.1

    a.sub.1 =a.sub.1 ×1+0

during two operation times; andsaid even term calculation means and said data distribution means cooperate to calculate the following terms

    a.sub.1 =a.sub.O ×b.sub.1 +c.sub.1

    a.sub.2 =a.sub.1 ×b.sub.2 +c.sub.2

during the same two operation times, andwherein at a normal operation time after the initial operation time, said odd term calculation means and said data distribution means cooperate to calculate each odd term of the following formula

    a.sub.j =a.sub.j-2 ×b.sub.j-1 ×b.sub.j +b.sub.j ×c.sub.j-1 +c.sub.j

where, j=3, 5, . . . , n in each operation time; andsaid even term calculation means and said data distribution means cooperate to calculate each even term of the following formula

    a.sub.k =a.sub.k-2 ×b.sub.k-1 ×b.sub.k +b.sub.k ×c.sub.k-1 +c.sub.k

where, k=4, 6, . . . , n+1 in each operation time.
 7. A vector processor according to claim 6, wherein each operation time comprises a plurality of operation cycles of said vector processor, the operation times are identical for calculating each term, and adjacent operation times for calculating adjacent terms are partially overlapped.
 8. A vector processor according to claim 7, wherein said data distribution means receives data from said odd and even third-stage data storage circuits and outputs the data to said vector storage access means.
 9. A vector processor according to claim 8,wherein said vector storage access means comprises a vector register unit for temporarily storing the input operands and the calculated odd and even terms, and wherein said data distribution means transfers the input operands and the calculated odd and even terms.
 10. A vector processor according to claim 2,wherein said at least one odd term feedback line of said odd term calculation means comprises a first feedback line, and first and second odd term data storage circuits connected in series for storing the calculated odd terms supplied through said first feedback line, wherein said odd term calculation means is formed so that(a) said first adding circuit receives an addend from a first selector of said plurality of selectors, (b) said first multiplication circuit receives a multiplier and a multiplicand from second and third selectors of said plurality of selectors, (c) said first adding circuit for receiving multiplied data from said first multiplication circuit, (d) said first odd term data storage circuit receives addition data from said first adding circuit, (e) said second odd term data storage circuit receives the addition data from said first odd term data storage circuit, (f) said first selector receives the constant data of zero, the second operand from said second buffer, and the addition data from said first odd term data storage circuit, (g) said second selector receives the constant data of zero, an initial data, the first and second operands, and the addition data from said first adding circuit through said first feedback line, and (h) said third selector receives the constant data of one, the first operand from said first buffer, and the addition data stored in said second odd term data storage circuit, wherein said at least one even term feedback line of said even term calculation means comprises a second feedback line, and first and second even term data storage circuits connected in series and for storing the calculated even terms supplied through said second feedback line, and wherein said even term calculation means is formed so that(i) said second adding circuit receives an addend from a fourth selector of said plurality of selectors, (j) said second multiplication circuit receives a multiplier and a multiplicand from fifth and sixth selectors of said plurality of selectors, (k) said second adding circuit for receiving multiplied data from said second multiplication circuit, (l) said first even term data storage circuit receives addition data from said second adding circuit, (m) said second even term data storage circuit receives the addition data from said first even term data storage circuit, (n) said fourth selector receives the constant data of zero, the second operand from said second buffer, and the addition data from said first even term data storage circuit, (o) said fifth selector receives the constant data of zero, the initial data, the first and second operands, and the addition data from said second adding circuit through said second feedback line, and (p) said sixth selector receives the constant data of one, the first operand from said first buffer, and the addition data stored in said second even term data storage circuit. 10,
 11. A vector processor according to claimwherein said odd term calculation means comprises:an odd first-stage first data storage circuit connected to said first selector, for temporarily storing data therefrom; odd first-stage second and third data storage circuits respectively connected between said second and third selectors and said first multiplication circuit, for temporarily storing data from said second and third selectors; an odd second-stage first data storage circuit connected between said odd first-stage first data storage circuit and said first adding circuit, for temporarily storing data from said odd first-stage first data storage circuit; an odd second-stage second data storage circuit having an input terminal connected to said first multiplication circuit and an output terminal connected to said first adding circuit, said odd second-stage second data storage circuit temporarily storing the multiplied data from said first multiplication circuit; and an odd third-stage data storage circuit connected between said first adding circuit and said first odd term data storage circuit through said first feedback line, for temporarily storing the addition data from said first adding circuit, and wherein said even term calculation means comprises:even first-stage first data storage circuit connected to said fourth selector, for temporarily storing data therefrom; even first-stage second and third data storage circuit respectively connected between said fifth and sixth selectors and said second multiplication circuit, for temporarily storing data from said fifth and sixth selectors; even second-stage first data storage circuit connected between said even first-stage first data storage circuit and said second adding circuit, for temporarily storing data from said even first-stage first data storage circuit; even second-stage second data storage circuit having an input terminal connected to said second multiplication circuit and an output terminal connected to said second adding circuit, and even second-stage second data storage circuit temporarily storing the multiplied data from said second multiplication circuit; and even third-stage data storage circuit connected between said second adding circuit and said first even term data storage circuit through said second feedback line, for temporarily storing the addition data from said second adding circuit.
 12. A vector processor according to claim 11,wherein, at an initial operation time,said odd term calculation means and said data distribution means cooperate to calculate the following terms

    a.sub.1 =a.sub.0 ×b.sub.1 30 c.sub.1

    a.sub.1 =a.sub.1 ×1+0

during two operation times; andsaid even term calculation means and distribution means cooperate to calculate the following terms

    a.sub.1 =a.sub.0 ×b.sub.1 +c.sub.1

    a.sub.2 =a.sub.1 ×b.sub.2 +c.sub.2

during the same two operation times, andwherein at a normal operation time after the initial operation time, said odd term calculation means and said data distribution means cooperate to calculate each odd term of the following formula

    a.sub.j =a.sub.j-2 ×b.sub.j-1 ×b.sub.j +b.sub.j ×c.sub.j-1 +c.sub.j

where, j=3, 5, . . . , n in each operation time; andsaid even term calculation means and said data distribution means cooperate to calculate each even term of the following formula

    a.sub.k =a.sub.k-2 ×b.sub.k-1 ×b.sub.k +b.sub.k ×c.sub.k-1 ×c.sub.k

where, k=4, 6, . . . , n+1 in each operation time.
 13. A vector processor according to claim 12, wherein each operation time comprises a plurality of operation cycles of said vector processor, the operation times are identical for calculation of each term, and adjacent operation times for calculating adjacent terms are partially overlapped.
 14. A vector processor according to claim 13, wherein said data distribution means receives data from said odd and even third-stage data storage circuits and outputs to data to said vector storage access means.
 15. A vector processor according to claim 14,wherein said vector storage access means comprises a vector register unit temporarily storing the input operands and the calculated odd and even terms, and wherein said data distribution means transfers the input operands and the calculated odd and even terms.
 16. A vector processing system for processing a modified recurrent equation having odd and even terms, the modified recurrent equation has a formula of a form

    a.sub.i =a.sub.i-2 ×b.sub.i-1 ×b.sub.i +b.sub.i ×c.sub.i-1 +c.sub.i

where i is an integer, said vector processing system including a storage unit for storing vector data, said vector processing system comprising: vector instruction control means for receiving vector instructions and for controlling processing of the vector instructions; vector storage access means for accessing the vector data from the main storage unit and for transferring calculated vector data to the main storage unit; vector calculation means, having an input end, for calculating the calculated vector data under control of said vector instruction control means, said vector calculation means includesat least one term calculation means for calculating the odd terms of the modified recurrent equation; and at least one even term calculation circuit means for calculating the even terms of the modified recurrent equation concurrently with the calculating of said at least one odd term calculation means; and data distribution means for supplying the vector data from said vector storage access means to said vector calculation means, and for temporarily storing and supplying the odd terms and the even terms calculated by said vector calculation means to the input end of said vector calculation means.
 17. A vector processing system for processing a modified recurrent equation having odd and even terms, the modified recurrent equation has a formula of a form

    a.sub.i =a.sub.i-3 ×b.sub.i-2 ×b.sub.i-1 ×b.sub.i 30 b.sub.i-2 ×b.sub.i-1 ×c.sub.i-2 +b.sub.i ×c.sub.i-1 +c.sub.i

where i is an integer, said vector processing system including a storage unit for storing vector data, said vector processing system comprising: vector instruction control means for receiving vector instructions and for controlling processing of the vector instructions; vector storage access means for accessing the vector data from the main storage unit and for transferring calculated vector data to the main storage unit; vector calculation means, having an input end, for calculating the calculated vector data under control of said vector instruction control means, said vector calculation means includesat least one odd term calculation means for calculating the odd terms of the modified recurrent equation; and at least one even term calculation circuit means for calculating the even terms of the modified recurrent equation concurrently with the calculating of said at least one odd term calculation means; and data distribution means for supplying the vector data from said vector storage access means to said vector calculation means, and for temporarily storing and supplying the odd terms and the even terms calculated by said vector calculation means to the input end of said vector calculation means. 